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Preliminary W89C926 PENTIC+ PCMCIA ETHERNET NETWORK TWISTED PAIR INTERFACE CONTROLLER
GENERAL DESCRIPTION
The W89C926 PENTIC+ is a CMOS device designed for easy implementation of PCMCIA R2.1 compatible CSMA/CD local area networks. The W89C926 combines a W89C902 Serial LAN Coprocessor for Twisted-pair (SLCT) with a PCMCIA Bus Interface (PBI), thus integrating into a single chip all the registers and logic necessary to connect the SLCT to buffer SRAMs, flash memories (or an EEPROM), and the PCMCIA system bus. The PCMCIA Bus Interface (PBI) is designed to provide a switchless setting architecture that allows the card setting to be configured by software. It implements a full set of PCMCIA registers for PCMCIA R2.1 compatibility and a set of configuration registers for switchless card setting. The card can be configured quickly and easily by modifying the contents of the configuration registers. The PENTIC+ can run with shared memory mode and NE2000TM I/O mode drivers on a 16-bit bus interface. No extra effort is needed to ensure software compatibility. The PENTIC+ provides a flexible flash memory (up to 128 KB)/EEPROM (up to 512 bytes) architecture for PCMCIA nonvolatile storage and an ID/Configuration auto-load architecture for power-on initialization. Vendors can store the Ethernet(R) ID, configuration, and CIS in the flash memory or EEPROM. The PENTIC+ will auto-load necessary information when power is switched on.
FEATURES
* * * * * * * * * *
Runs with NE2000 TM or shared memory drivers Supports up to 128 KB flash memory (8K/112K for attribute/common memory) or 512 bytes EEPROM (for attribute memory only) for nonvolatile memory Uses one 16 KB SRAM or one 32 KB SRAM (if EEPROM is used) for 16 KB Ethernet ring buffer Auto-load algorithm provided for power-on initialization Supports necessary PCMCIA registers Configuration registers allow switchless card setting UTP/BNC auto media-switching function provided Drives necessary LEDs for network status display Single 5V power supply with low power consumption 100-pin thin package (TQFP) fits into PCMCIA Type II profile
Ethernet(R) is a registered trademark of the Xerox Corporation. NE2000TM is a trademark of Novell, Inc.
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Publication Release Date: January 1996 Revision A1
W89C926 PENTIC+
PIN CONFIGURATION
E E C S M/ M , SMS/ / AS ARF 1R1CC 1D0SS
M S D 7
M S D 6
M S D 5
M S D 4
M S D 3
M S A 1 6
M S AC CRRT 1 D DXXX 5+-+-+
A TG XN -D
/ G D AT TRR L VX XX XG CO OI I N XX N C+ - + - D12K
/ A C T L E D
T H I N
87 09 MSA9 MSA8 VCC MSA13 GND MSWR MSD2 MSD1 MSD0 MSA0 MSA1 MSA2 MSA3 MSA4 MSA5 MSA6 MSA7 MSA12 MSA14 IOS16 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
777 876
7 5
77 43
77 21
76 09
6 8
66 76
6 5
666 432
66 10
5 9
55 87
5 6
555 543
5 2
5 1 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 3 0
HD3 HD4 HD11 HD5 HD12 VCC HD6 GND HD13 HD7 HD14 CE1 HD15 HA10 CE2 OE HA11 IORD HA9 IOWR
.
1
23
4
5
67
8
1 90
111 123
111 456
111 789
2 0
2 1
2 2
2 3
2 4
22 56
2 7
22 89
HHVHGHHHHH/ H/ DDCDNDDDAARAI 12C9D1800 1E2N 0 P G A C K
DHD/ HRHHHH GA V WA E A A A A N3CA4S56 71 2 E CI D T T
H A 1 5
H A 1 6
// IW RE E Q
H A 1 4
HH AA 18 3
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W89C926 PENTIC+
PIN DESCRIPTION
NAME HA0-2 HA3, 4 HA5-7 HA8-10 HA11-13 HA14-16 HD0-2 HD3-5 HD6-8 HD9-11 HD12-15 IREQ NUMBER 9, 10, 12 15, 18 20-22 30, 32, 37 34, 23,29 28, 24, 25 8, 6, 2 50, 49, 47 44, 41, 7 4, 1, 48 46, 42, 40, 38 26 O/TTL Interrupt Request: IREQ is asserted by the PENTIC+ to request host service. During auto-loading, which is caused by a H/W reset, IREQ will assert low until auto-loading is complete. This signaling is used as Rdy/-Bsy of Memory Only Interface during initialization, according to PCMCIA R2.1. I/O Read: IORD is asserted by the system to read data from the card's I/O space. It has an internal 100K ohm pull-high resistor. IOWR 31 I/TTL I/O Write: IOWR is asserted by the system to write data to the card's I/O space. It has an internal 100K ohm pull-high resistor. WE 27 I/TTL Write Enable: The WE input is asserted by the system to strobe memory write data into the card memory. It has an internal 100K ohm pull-high resistor. IO/3SH Host Data Bus: Bidirectional host data bus. TYPE I/TTL Host Address Bus: Host address lines used to decode access to the card's memory and I/O spaces. DESCRIPTION PCMCIA Bus Interface
IORD
33
I/TTL
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Publication Release Date: January 1996 Revision A1
W89C926 PENTIC+
Pin Description, continued
NAME OE
NUMBER 35
TYPE I/TTL Output Enable:
DESCRIPTION
The OE line is asserted by the system to obtain memory read data from the card memory. It has an internal 100K ohm pull-high resistor.
CE1 ,2
39, 36
I/TTL
Card Enable:
CE1 are asserted by the system for data bus width ,2 control as shown below. These pins have an internal 100K ohm pull-high resistor.
CE2 0 0 1 1 REG 11 I/TTL
CE 0 1 0 1
HD15-HD8 Valid Valid High-Z High-Z
HD7-HD0 Valid High-Z Valid High-Z
Register & I/O selection: REG is asserted by the system to access attribute memory or I/O space. It remains high inactive for common memory accesses. It has an internal 100K ohm pull-high resistor.
IOIS16
100
O/TTL
16-bit I/O access: Asserted by the PENTIC+ to inform the system that current operation is a 16-bit I/O access.
INPACK
13
O/TTL
Input Acknowledge: Asserted by the PENTIC+ when it has been selected and can respond to an I/O read cycle.
WAIT
17
O/TTL
Wait State: Asserted by the PENTIC+ to insert wait states into current memory or I/O access cycles.
RESET
19
I/TTL
Card Reset: A RESET pulse will initiate the PENTIC+'s initialization procedure, including auto-ID/configuration loading, register initialization, and state machine initialization. The pulse width should be at least 500 nS to be recognized as a valid reset. This pin has an internal 100K ohm pull-up resistor.
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W89C926 PENTIC+
Pin Description, continued
NAME MSA0-7 MSA8-10 MSA11-13 MSA14-16 MSD0-2 MSD3-7
NUMBER 90-97 82, 81, 78 80, 98, 84 99, 69, 70 89-87 71-75
TYPE O/TTL
DESCRIPTION Memory Support Address: Latched address used to decode accesses to the onboard memory.
Memory Support Interface
IO/3SH I/O/3SH
Memory Support Data Bus: Bidirectional on-board memory data bus. EEPROM Interface: During the EEPROM auto-load or read/write sequence, MSD0 is used as a serial data input/output from/to EEPROM, MSD1 outputs EEPROM commands to EEPROM, and MSD2 sends a clock with a period of 1.2 microseconds. This function is available only when EECS/ FCS is low during H/W reset.
RCS
77
O/TTL
SRAM Chip Select:
RCS is asserted by the PENTIC+ for SRAM chip enable during buffer memory access.
EECS/ FCS
76
O/3SH
Nonvolatile Memory Chip Select: EECS/ FCS is asserted by the PENTIC+ for chip enable during nonvolatile memory access. It is active low for flash memory enable and active high for EEPROM chip enable.
I/3SH
Nonvolatile Memory Detection: During H/W reset, the PENTIC+ will determine the existing nonvolatile memory type by sampling the voltage level on this pin. If this pin is externally pulled high with a 470K ohm resistor, the PENTIC+ will determine that the memory is a flash memory; if the pin is pulled low with a 470K ohm resistor, it will determine that the memory is an EEPROM.
MSRD
79
O/TTL
Memory Support Read:
MSRD is asserted by the PENTIC+ to strobe read data from the on-board memory. Both SRAM and flash memory use MSRD as the read command strobe.
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Publication Release Date: January 1996 Revision A1
W89C926 PENTIC+
Pin Description, continued
NAME MSWR
NUMBER 86
TYPE O/TTL
DESCRIPTION Memory Support Write: MSWR is asserted by the PENTIC+ to strobe write data into the on-board memory. Both SRAM and flash memory use MSWR as the write command strobe.
Network Interface TXO+, 60, 59 O/DIF Twisted Pair Transmit Outputs: UTP differential output pair. A 1.21 K precision resistor should be shunted across these pins for signal preequalization. Twisted Pair Receive Inputs: These inputs are fed into a differential amplifier which passes valid data to the LCE core. A 100 precision resistor should be shunted across these pins for impedance matching. AUI Transmit Outputs: Differential transmit outputs. These pins should be connected to 270 ohm external pull-down resistors. AUI Receive Inputs: Differential receive input pair from AUI interface. AUI Collision Inputs: Differential collision input pair from AUI interface. Crystal Input: Master 20 MHz clock input. Crystal Feedback Output: This pin should be connected to the crystal when a crystal is used and should be left unconnected when an oscillator is used. Thin Cable Select: This pin is high when the PENTIC+ is configured for thin cable media. It can be used as a switch to DC-DC converter for network media selection. Activity: This output asserts low for approximately 50 mS whenever the PENTIC+ transmits or receives data without collisions. This output can also be controlled by the power-down state machine; refer to the descriptions of the COR and CFA registers for more details.
RXI+, -
58, 57
I/DIF
TX+, -
64, 63
O/DIF
RX+, CD+, X1 X2
66, 65 68, 67 55 54
I/DIF I/DIF I/XTAL O/XTAL
THIN
51
O/TTL
ACTLED
52
O/TTL
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W89C926 PENTIC+
Pin Description, continued
NAME GDLNK
NUMBER 53
TYPE O/TTL GoodLink:
DESCRIPTION This output asserts low if the PENTIC+ is in TPI mode, link checking is enabled, and the link integrity is good or if link checking is disabled; otherwise, is not asserted. This output can also be controlled by power down state machine; refer to the description of the COR and CFA registers for more details.
Power Pins AVCC 61 Analog Power Supply Pins: These pins supply +5V to the PENTIC+'s analog circuitry for the network interface. Analog layout rules and decoupling methods must be applied between this pin and AGND. AGND VCC 62 3, 16, 45, 83 Analog Ground Pins: These pins are the ground to the analog circuitry. Digital Power Supply Pins: These pins supply +5V to the PENTIC+'s digital circuitry. GND 5, 14, 43, 56, 85 Digital Ground Pins: These pins are the ground to the digital circuitry.
Note: I: input pin; O: output pin; IO: bidirectional input/output pin; TTL: TTL level buffer stage; ODH: open drain buffer stage; MOS: MOS level buffer stage; 3SH: Tri-state buffer stage; DIF: differential buffer stage, XTAL: crystal.
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Publication Release Date: January 1996 Revision A1
W89C926 PENTIC+
BLOCK DIAGRAM
ID Registers
EEPROM Control
Flash Memory Control
Buffer Memory Control
W89C902 Core
Local Bus
Config. Registers & Control
Interrupt Control
Local Bus Arbiter
PCMCIA Bus Interface Logic and Drivers
HA0-16
HD0-15
PCMCIA slot
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W89C926 PENTIC+
SYSTEM DIAGRAM
SRAM 16 KB X 1 or 32KB X 1 (EECS/FCS pull low) 15 OSC/XTAL
MSD0-7 EEPROM 93C56/66 (EECS/FCS pull low) 3 MSA0-16 W89C926
TP/IF LEDs W89C92 optional
FLASH 128KB X 1 (EECS/FCS pull high) PCMCIA slot HA0-16 HD0-15
Two combinations may be used for the hardware structure: Combination 1: EECS/FCS pull high/128 KB X 1 flash memory/16 KB X 1 SRAM Combination 2: EECS/FCS pull low/256 or 512B EEPROM/32 KB X 1 SRAM
FUNCTIONAL DESCRIPTION
ADDRESS MAPPING
EEPROM MAPPING EEPROM ADDRESS 00H 01H 02H 03H 04H 05H 06H-08H 09H 0AH-nH (n+1) H-FFH HIGH BYTE CFB ID-1 ID-3 ID-5 Check Sum 57H CIS LOW BYTE Word Count CFA ID-0 ID-2 ID-4 Board Type (05H) 57H CIS -
Notes: 1. The fifth (05H) word is used for shared memory mode and the ninth (09H) word is used for NE2000 mode. 2. Word Count = nH (n should be set as a non zero value, a zero value will cause an unpredicted error).
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Publication Release Date: January 1996 Revision A1
W89C926 PENTIC+
ATTRIBUTE MEMORY MAPPING EECS/FCS Pull High (Flash Memory) ATTRIBUTE MEMORY OFFSET (HA0-16) 00000H 00F9EH 00FA0H 00FA2H 00FA4H 00FA6H 00FA8H 00FAAH 00FACH 00FAEH 00FB0H 00FB2H 00FB4H 00FB6H 00FB8H 00FBAH 00FBCH 00FBEH 00FC0H 00FC2H 00FD0H 00FD2H 00FD4H 00FD6H 00FF0H 00FF2H 00FF4H 00FF6H 00FFEH 01000H 03FFEH Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Flash Register Register Register Register Register Register Register Register Register Flash CIS ID-0 ID-1 ID-2 ID-3 ID-4 ID-5 Board Type (05H) Check Sum 57H 57H CFA CFB COR CCSR SCR Reserved (see note) CFA CFB SR Reserved CIS TYPE CONTENTS
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W89C926 PENTIC+
EECS/FCS Pull Low (EEPROM) ATTRIBUTE MEMORY OFFSET (HA0-16) 00000H 003D6H 00FD0H 00FD2H 00FD4H 00FD6H 00FF0H 00FF2H 00FF4H 00FF6H 00FFEH 01000H 03FFEH TYPE Memory (SRAM) Unsued Register Register Register Register Register Register Register Register Register Unused CONTENTS CIS COR CCSR SCR Reserved (see note) CFA CFB SR Reserved -
Notes: 1.The reserved register space in the attribute space is left for future extension. Users should not place their application in this area. 2. When EECS/ FCS is pulled high, address 00FA0H to 00FFEH is used for Ethernet ID, configuration, and registers. Vendors should not put CIS in this region. 3. When EECS/ FCS is pulled low, Address 00000H to 003D6H is read-only. The PENTIC+ will ignore write accesses to this area.
NE2000 Mode Mapping
I/O Mapping SYSTEM I/O OFFSET (HA0-4) 00H 0FH 10H 17H 18H 1FH NAME LCE Core Registers Remote DMA Port Reset Port OPERATION Register Read/Write Remote DMA Read/Write Software Reset
Notes: 1. The PENTIC+ decodes only HA0-4 for I/O access, so the IOBase address is left for the host adapter and the socket service to determine. 2. To issue a S/W reset, simply issue an I/O read to the Reset Port. The PENTIC+ will assert a 600 nS internal reset pulse to reset the core state machine. If the host tries to access the PENTIC+, WAIT will be asserted low until the reset is completed.
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Publication Release Date: January 1996 Revision A1
W89C926 PENTIC+
Buffer Memory Mapping NIC CORE MEMORY MAP 0000H 001FH 0020H 00FFH 0100H 3FFFH 4000H 7FFFH 8000H BFFFH C000H FFFFH Nonvolatile Memory Mapping F/ EE = 1 (flash memory used) SYSTEM OFFSET (HA0-16) 00000H 03FFFH 04000H 1FFFFH Attribute/ Flash Common/ Flash (112K x 8) CIS/ID/PCMCIA Register (8K x 8) MEMORY TYPE NAME NE2000 COMPATIBLE ID Registers Aliased ID Registers Buffer SRAM (16K x 8) Aliased ID Registers Aliased Buffer SRAM
F/ EE = 0 (EEPROM used) SYSTEM OFFSET (HA0-16) 00000H 003D6H Attribute/ (Note) CIS (492 x 8) MEMORY TYPE NAME
Notes: 1. This attribute memory is an image from EEPROM. It is actually resident in upper half of the SRAM after power-on autoloading. 2. Refer to "Attribute Memory Mapping" for detailed locations. 3. The PENTIC+ decodes HA0-16 for memory access. The (common or attribute) MEMBase addresses are left for the host adapter and the socket service to determine.
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W89C926 PENTIC+
Shared Memory Mode Mapping
I/O Mapping SYSTEM I/O OFFSET (HA0-4) 00H 01H 05H 08H 0FH 10H 1FH
Notes: 1. The PENTIC+ decodes only HA0-4 for I/O access, so the IOBase address is left for the host adapter and the socket service to determine. 2. MMA and MMB are used for shared memory mapping control. Since the PENTIC+ decodes only MSA = 0000H to 03FFFH for shared memory that is, the shared memory base address for the PENTIC+ is 00000H, MMB and bit 0 to 5 of MMA should be set to 0. 3. Since the PENTIC+ supports 16-bit mode only, the Word/-Byte will be read as 01H.
NAME MMA Word/-Byte MMB ID Registers LCE Core Registers
OPERATION I/O Write I/O Read I/O Write I/O Read Register Read/Write
Buffer Memory Mapping SYSTEM OFFSET (HA0-16) 00000H 03FFFH 04000H 07FFFH
Notes: 1. This region is occupied by flash memory. 2. The PENTIC+ decodes HA0-16 for memory access. The (common or attribute) MEMBase addresses are left for the host adapter and the socket service to determine.
MEMORY TYPE Common/SRAM Common/(Note)
SHARED MEMORY MODE Buffer SRAM (16K x 8) Unused
Nonvolatile Memory Mapping F/ EE = 1 (flash memory used) SYSTEM OFFSET (HA0-16) 00000H 03FFFH 04000H 1FFFFH Attribute/ Flash Common/ Flash CIS/ID/PCMCIA Register (8K x 8) (112K x 8) MEMORY TYPE NAME
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Publication Release Date: January 1996 Revision A1
W89C926 PENTIC+
F/ EE = 0 (EEPROM used) SYSTEM OFFSET (HA0-16) 00000H 003D6H
Notes: 1. This attribute memory is an image from EEPROM. It is physically resident in upper half of the SRAM after power-on autoloading. 2. Refer to "Attribute Memory Mapping" for detailed locations. 3. The PENTIC+ decodes HA0-16 for memory access. The (common or attribute) MEMBase addresses are left for the host adapter and the socket service to determine.
MEMORY TYPE Attribute/ (Note)
NAME CIS (492x 8)
REGISTER FILE
The W89C926 PENTIC+ has four register sets: the core register set, the PCMCIA configuration register set, the LAN configuration register set, and the special control register set. The core register set is the same as that in the W89C90 and will not be discussed here. The other three register sets are described below.
PCMCIA Configuration Register Set
The PENTIC+ provides three PCMCIA configuration registers needed to ensure compatibility with various operating systems. COR (Configuration Option Register) Access Address: AMBase + 00FD0H Access Type: Attribute Memory Read/Write BIT 0-5 SYMBOL IDX0-5 DESCRIPTION Configuration Index These six bits are used to indicate entry of the card configuration table located in the CIS (Card Information Structure; refer to PCMCIA R2.1). These bits are 0 at power-on. Reserved, must be 1 (level mode interrupt) when read. S/W Reset A software reset is issued when a 1 is written to this bit. This is the same as a H/W reset except that this bit and the necessary information (CFA, CFB, CIS, and Ethernet ID) are not cleared, and the auto-load procedure is not performed. Returning a 0 to this bit will leave the PENTIC+ in a post-reset state the same as that following a hardware reset. The value of this bit at power-on is 0.
6 7
SRESET
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W89C926 PENTIC+
CCSR (Card Configuration and Status Register) Access Address: AMBase + 00FD2H Access Type: Attribute Memory Read/Write BIT 0 1 SYMBOL Intr DESCRIPTION Reserved, must be 0. Interrupt Status This bit indicates the internal status of an interrupt request. It remains high until the condition that caused the interrupt request has been serviced. This bit is 0 at power-on. Reserved, must be 0s.
2-7
-
SCR (Socket and Copy Register) The SCR is used to enable the PENTIC+ to distinguish between similar cards installed in the same system. Access Address: AMBase + 00FD6H Access Type: Attribute Memory Read/Write BIT 0-3 SYMBOL SocNum Socket Number Set these bits to indicate to the PENTIC+ that it is located in the n'th socket. The first socket is numbered 0. This permits any cards designed to do so to share a common set of IO ports while remaining uniquely identifiable. These bits are 0 at power-on. 4-6 CopNum Copy Number Set these bits to indicate to the PENTIC+ that it is the n'th copy of another card installed in the system that is configured identically. The first identical card should be assigned a value of 0 as its copy number. This permits any cards designed to do so to share a common set of I/O ports while remaining uniquely identifiable and consecutively ordered. These bits are 0s at power-on. 7 Reserved, must be 0. DESCRIPTION
LAN Configuration Register Set
These two registers are used for LAN configuration control. CFA (Configuration Register A) This register is used to select the PENTIC+'s operating mode and LED control. Access Address: AMBase + 00FF0H Access Type: Attribute Memory Read/Write
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Publication Release Date: January 1996 Revision A1
W89C926 PENTIC+
BIT 0 SYMBOL M/-IO DESCRIPTION Share Memory/IO Mode Select The PENTIC+ will operate in shared memory mode if this bit is high; otherwise, it will be in I/O mode. Reserved, must be 0s. Flash or EEPROM Select. This bit directly reflects the sampled value on pin EECS/FCS during a H/W reset. This bit will be high or low if EECS/FCS is pulled high or low. This bit is read-only. LED Disable. Setting this bit high disables the LED indicators in order to save power.
1-5 6
F/ EE
7
LED
CFB (Configuration Register B) Access Address: AMBase + 00FF2H Access Type: Attribute Memory Read/Write BIT 0-1 SYMBOL PHY01 DESCRIPTION Physical Media Select These two bits determine to which type of medium the PENTIC+ is attached. The THIN pin will output low in 10BASE5 mode and high in 10BASE2 mode, according to PHY0,1. This can be used to control the DC-DC converter for electrical isolation. PHY1 PHY0 Attached Medium Type 0 0 1 1 0 1 0 1 TPI (10BASE-T Compatible Squelch Level) Thin Ethernet (10BASE2) Thick Ethernet (10BASE5) TPI (Reduced Squelch Level)
The PENTIC+ also provides a UTP/BNC auto media-switching function. The physical interface will jump from UTP to BNC when the PENTIC+ is configured at UTP, the link checking is enabled, and the UTP path is broken. It will jump back immediately if the UTP path has been reconnected. When the physical interface is not configured at TPI or the link checking is disabled, the auto media-switching function will be disabled.
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W89C926 PENTIC+
CFB (Configuration Register B), continued
BIT 2
SYMBOL LNKEN
DESCRIPTION Link Enable Writing a "1" to this bit will disable the link pulse generation, auto mediaswitching function, and link integrity check function. Writing a "0" to this bit will enable these functions. Link Status This bit indicates the present link status. It is high if the PENTIC+ is in TPI mode, the link checking is enabled, and the link integrity is good or if the link checking is disabled; otherwise, it is low. IOIS16 Timing Control. If this bit is set high, the IOIS16 signal will decode CE1,2 ; otherwise, IOIS16 is decoded according to HA and REG (default). Flash Write Enable. The default setting for the flash memory is write-protected. If FWEN = 1, the PENTIC+ allows the flash to be written to. The write command and chip select signal is prohibited if FWEN = 0. SRAM Speed Select. If SRAMSEL = 1, the SRAM-15 is selected. Otherwise, SRAM-70 is used. The default is SRAM-70. Reserved.
3
LNKSTS
4
IO16CON
5
FWEN
6
SRAMSEL
7
-
Special Control Register Set
These registers are used for special checking or EEPROM access control. Signature Register (SR) A signature register is used for identification so that the software driver can easily distinguish between different chips. The content can be read out in toggled order as follows: Access Address: AMBase + 00FF4H Access Type: Attribute Memory Read MSB LSB (2N)th time: (2N-1)th time: 10001000 00000000 where N = 1, 2, ... (after H/W reset)
EEPROM Access Register (EEAR) This register is located on page 3 and is used for EEPROM read/write access control. It is inhibited when EECS/FCS is pulled high. Access Address: IOBase + 02H Access Type: I/O Read/Write
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Publication Release Date: January 1996 Revision A1
W89C926 PENTIC+
BIT 0-5 6 SYMBOL EW/ ER Reserved. Must be 0s. EEPROM Write/Read Select. This bit selects the EEPROM read/write sequence. If EW/ER = 1, the write sequence is selected. If EW/ER = 0, the read sequence is selected. 7 EOS EEPROM Operation Select. This bit enables the EEPROM read/write sequence. If EOS = 1, the EEPROM read/write sequence will be started. EOS is reset if the read/write sequence is finished or aborted. DESCRIPTION
EEPROM Address/Data Register (ADR) This register is located on page 3 and is used for EEPROM address or data transfer during EEPROM access. Access Address: IOBase + 04H Access Type: I/O Read/Write
POWER-ON INITIALIZATION AND AUTO-LOADING PROCESS
When powered on, the system should reset the card first, as required by the PCMCIA specifications. The reset signal will trigger a number of internal operations: First, the PENTIC+ monitors the EECS/FCS pin to determined where the configurations are stored. If this pin is pulled high, the configurations are stored in the flash memory; if it is pulled low, they are stored in an EEPROM. Then, within 10ms after the reset pulse is negated, the PENTIC+ will automatically load the configurations, ID, and CIS data into the LAN configuration registers and the upper half of SRAM (if an EEPROM is used). During this auto-load procedure the PENTIC+ will assert IREQ low for Rdy/Bsy signaling, since the socket is configured at the memory-only interface during initialization. Note that this auto-load operation occurs only after a hardware reset pulse. A software reset (including setting COR.SRESET = 1) will not invoke this operation.
EECS/FCS Pulled High
If EECS/ FCS is pulled high, this indicates that the configurations are stored in a flash memory. Accordingly, after a power-on reset the PENTIC+ will automatically load the LAN configuration registers from flash memory. The Ethernet IDs stored in the flash memory will be mapped into ID registers automatically when they are read.
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W89C926 PENTIC+
TR > 500 nS RESET
IREQ (Rdy/Bsy) TCE > 20 mS CE1,2 TS > 150 S F/EE sampling FCS MSRD MSD0-7 MSAn TAUTO < 5 mS
TFR > 150 nS MSAn flash address
TFOZ > 60 nS
TFR > 150 nS flash address
TFOZ > 60 nS
FCS
MSRD
MSD0-7
EECS/FCS Pulled Low
If EECS/ FCS is pulled low, this indicates that the configurations, Ethernet ID, and CIS are stored in an EEPROM. In this case, after a power-on reset the PENTIC+ will load the configurations into the LAN configuration registers and the Ethernet IDs and CIS into the higher half of SRAM memory (with auto-mapping to ID registers and attribute memory space, respectively). Since the EEPROM used is a 93C66, a serial EEPROM storage device, the access time is quite long and the system has to wait for the loading sequence (refer to PCMCIA R2.1). Loading a word of EEPROM typically takes 34 S. The exact time for EEPROM loading depends on the length of CIS but must not exceed 10 mS.
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Publication Release Date: January 1996 Revision A1
W89C926 PENTIC+
TR > 500 nS RESET
IREQ (Rdy/Bsy) TCE > 20 mS TAUTO < 10 mS TS > 150 S F/EE sampling EECS, RCS MSWR MSD0-7 MSAn
CE1,2
TEEOZ > 0.5 S TEER > 32 S MSAn TSW > 100 nS even address
TSOZ > 20 nS TSW > 100 nS odd address
TSOZ > 20 nS
EECS
MSD0-2 16 bit EEload MSD0-7 low byte RCS high byte
MSWR
EEPROM Contents Load Back
When an EEPROM is used to store CIS, the PENTIC+ allows the contents of the EEPROM to be modified by means of the following sequence: write (EEAR, EOS = 1 EW/ER = 1) write (ADR, address); write (ADR, word_data); wait ( ); repeat ( read(EEAR, EOS); ) until (EOS = 0); /* The entire sequence should be consecutive or the process will be aborted. */
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W89C926 PENTIC+
The ADR register located at page3 04H of the core controller is used as a temporary register for EEPROM read/write. When the EEPROM load-back sequence specified above is performed, the content of the specified address will be overwritten by the new data. Note that since the EEPROM is word-aligned, each time the sequence is performed one word of data is modified. The address range available is from 00H to ffH. To make sure that the EEPROM is written correctly, the programmer can use the following read-check process to read a word from a specified address in the EEPROM. write (EEAR, EOS = 1 EW/ER = 0); write (ADR, address); wait ( ); repeat ( read(EEAR, EOS); ) until (EOS = 0); read(ADR); /* read word data */ /* The entire sequence should be consecutive or the process will be aborted. */ Note that data will be kept in the ADR until they are updated. That is, the data can be read out any time afterwards unless new data have been written.
SRAM Physical Map
When an EEPROM is used for attribute memory storage, the 32K byte SRAM has two roles in the PENTIC+ design: the first 16K bytes of SRAM serve as an Ethernet buffer ring, while the remainder is used for temporary storage of Ethernet IDs and CIS storage (if EECS/FCS is pulled low). The detailed physical mapping of the SRAM memory is shown in the table below. When a flash memory is used, only a 16K byte SRAM is needed to serve as the Ethernet ring buffer. SRAM Physical Address 0000H3FFFH 4000H 4001H 4002H 4003H 4004H 4005H 4006H 4007H 4008H400DH 400EH 400FH 4010H41FBH 41FCH7FFFH EECS/ FCS pull low Ethernet Buffer ID0 ID1 ID2 ID3 ID4 ID5 Board Type (05H) Checksum 57H 57H CIS EECS/ FCS pull high Ethernet Buffer
Unused
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Note that if EECS/FCS is pulled low, the CIS is stored in the SRAM starting at address 4010H. The length of the CIS depends on the word count specified in the first byte of EEPROM. During a poweron reset, the PENTIC+ will load the exact word count specified in the EEPROM rather than read in all bytes in the EEPROM. The PENTIC+ will automatically translate the address from the host if the host tries to read CIS. It will translate the attribute memory address by assuming that the first CIS byte is stored at 00H of attribute memory, the second CIS byte is stored at 02H, and so forth. Users should assign CIS accordingly, or else the CIS may be lost. Also note that for auto-load information write protection, the PENTIC+ will ignore any write operation above 4000H of SRAM. If it is necessary to change the settings, users should do so by writing the flash memory or EEPROM. Minimal System Design A low-cost, dedicated LAN card can be designed using the PENTIC+ chip, a 32K x 8 SRAM, a serial EEPROM (93C66/93CS66), and a pig tail for the network interface MAU, along with certain other peripheral components. The following is a sample CIS table that can be used with this minimal system design: 01 03 dc 03 ff 17 03 5b 09 ff 1a 05 01 01 e0 1f 0f 1b 13 c1 c1 7d 19 55 15 26 00 33 43 16 45 70 ff ff 48 40 00 00 14 00 f0 09 'WinICard' ff 21 02 06 03 20 04 u00 u01 u02 u03 15 14 04 01 u04 u05 u06 u07 u08 u09 u10 u11 u12 u13 u14 u15 u16 u17 u18 u19 00 ff ff ff
FLASH MEMORY ACCESS
The flash access and the buffer SRAM share the same memory support bus. The address pins of the flash memory are directly connected to MSA bus and data are accessed through the MSD bus. EECS/FCS is active low if it is pulled high and the attribute memory is accessed in the range 00000H to 03FFFH or the common memory is accessed in the range 04000H to 1FFFFH. Note that CFB.FWE should be set to 1 before a flash write command is issued.
I/O MODE OPERATION
The I/O mode provides two DMA channels for system access. The remote DMA moves data between system memory space and local memory space. The local DMA moves data between the FIFO of the SLCT and local memory space. However, since the SLCT can handle local DMA operations without system intervention (refer to the data sheet for the SLCT), the system has to perform only remote DMA reads/writes. In a transmit operation, the data should first be moved from the system to local buffer memory. This is simply an "OUT" command on the PC. Then the system orders the SLCT to start transmission, and the local DMA starts to move data from buffer memory to the transmit FIFO for transmission. In a receive operation, the local DMA moves received data from the receive FIFO to the buffer and asserts IREQ to the system when the buffer ring needs to be serviced. The system must move data - 22 -
W89C926 PENTIC+
out before the buffer ring overflows. This is done through a remote DMA read operation, which is simply a "IN" command on the PC.
SHARED MEMORY MODE OPERATION
In this mode, the local memory is mapped as part of the system memory. When it requires data transmission, the host fills the transmit buffer SRAM by a memory move operation and then issues a transmit command to the PENTIC+. When it receives data, the PENTIC+ will generate an interrupt to the host by asserting IREQ when one or more packets have been received. The PENTIC+ will then place the packets into the shared memory. The host should check the shared memory and remove the data before the buffer ring overflows. Bus arbitration is performed between the host and LCE core for shared memory usage. When memory accesses are issued, the arbiter will grant the bus master an acknowledge signal, which is a BACK to the LCE or a WAIT signal to the host. There is no predefined priority in the PENTIC+; bus arbitration is performed on a first-come, first-served basis. To implement the shared memory mode, the PENTIC+ uses memory mapping register A (MMA) and memory mapping register B (MMB) for memory mapping control. Since the PENTIC+ will operate in 16-bit shared memory operation at shared memory base address 00000H only, 0s should be written to MMB and bit 0 to 5 of MMA. The contents of the MMA are described below. MMA (Memory Mapping Register A) MMA is used for memory enable and software reset. It is located in I/O space, 00H, and can be accessed only in shared memory mode. Access Address: IOBASE + 00H Access Type: write-only BIT 0-5 6 SYMBOL MEN DESCRIPTION Reserved. Should be set to 0. If this bit is high, the buffer memory may be accessed by the system; if it is low, the buffer memory access is disabled. This bit is 0 at power-on. A shared memory mode software reset is issued when a 1 is written to this bit. Writing a 0 to this bit will clear the software reset. This bit is 0 at power-on.
7
SRESET
AUTO MEDIA-SWITCHING FUNCTION
The PENTIC+ also provides a user-friendly auto media-switching function. If the PENTIC+ is configured at the TPI, link checking is enabled, and the UTP link is broken, the PENTIC+ will detect the link status and switch to the BNC port immediately. After the UTP link is repaired, the PENTIC+ will detect the good link and switch back to the TPI again. If, however, the PENTIC+ is not configured at the TPI or link checking is disabled, the auto mediaswitching function will be disabled.
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BUS ARBITRATION AND STATE DIAGRAM
The PENTIC+ handles bus arbitration automatically. It can operate in four modes: idle state, slave read/write mode, DMA mode, and shared memory mode. The PENTIC+ controls the on-board devices by decoding these modes. At power-on, the PENTIC+ is in idle mode. If a register read/write command is issued, the PENTIC+ enters the slave read/write mode. If a local DMA or remote DMA (I/O mode only) is initiated by the PENTIC+ core coprocessor, the PENTIC+ enters DMA mode. A memory command will place the PENTIC+ in memory mode. At any given time, the PENTIC+ can be in only one state. The PENTIC+ handles state changes automatically. However, two events, such as a DMA command and a memory command, may be requested at the same time; in this case, the PENTIC+ allocates the bus on a firstcome, first-served basis. No predefined priority is set within the PENTIC+.
Register access Core Power-on Reset Idle access DMA operation Slave read/ write
Memory Memory operation access
In cases where the system has no authority on the requested bus, the PENTIC+ will drive the WAIT pin low so that the system can insert wait states. After the PENTIC+ has released the bus authority, WAIT is deasserted to instruct the system to stop inserting wait states.
SLCT CORE FUNCTION
The SLCT core coprocessor has five major logic blocks that control Ethernet operations: the register files, transmit logic, receive logic, FIFO logic, and DMA logic. The relationship between these blocks is depicted in the following block diagram.
PCMCIA Slot Interface
DMA Interface Logic
Transmit Logic 16-byte FIFO Receive Logic
SNA TX/RX Logic
Register File
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W89C926 PENTIC+
Core Register Files
The register files of the SLCT can be accessed by means of IO commands. The PENTIC+ should be in slave mode when the system accesses the register files. The command register (CR) determines the page number of the register file, while the system address HA<0:4> selects one register address from 01H to 0FH (I/O mode) or from 10H to 1FH (shared memory mode). The PCMCIA IORD and IOWR are the read/write commands used to activate the I/O operations. Refer to the W89C90 data sheet for more detailed information on the registers. DMA Interface Logic In I/O mapping mode, the SLCT provides two types of DMA operations, local DMA and remote DMA. In shared memory mode, only local DMA is available. Local DMA The local DMA transfers data from/to the on-board buffers. To perform data reception or transmission from/to remote nodes in the network, data must be moved from/to the FIFO. To enhance the efficiency of the transmission, the local DMA transfers data in batches: data are first collected and then moved in a batch. Up to 12 bytes of data can be moved in each transfer. This scheme reduces time wasted in requesting the bus. A local DMA begins by requesting the local bus. If the local bus is available to the SLCT core, the bus arbiter inside the PENTIC+ responds at once by asserting the bus acknowledge (BACK, refer to LCE); if, on the other hand, the bus is currently authorized to another device, the arbiter will not assert the bus acknowledge and the SLCT must wait. Note that this sequence will not affect the host system or system bus signals. After each batch of data is transferred, the SLCT checks the FIFO threshold levels to determine if another batch transfer should be requested. Remote DMA A remote DMA can be performed only in I/O mode. The remote DMA moves data between the host and the local buffers. Unlike a local DMA, the remote DMA is word-wide: the remote DMA operation transfers one word each time. Since a remote DMA is simply a system I/O operation, it sometimes affects the system bus. If the remote DMA is interleaved with other devices, WAIT is asserted to force the system to insert wait states. The PENTIC+ will automatically handle any arbitration necessary.
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FIFO Logic The SLCT has a 16-byte FIFO, which acts as an internal buffer to compensate for differences in the transmission/reception speed of different DMAs. The FIFO has FIFO threshold pointers to determine the level at which it should initiate a local DMA. The threshold levels, Which are different for reception and transmission, are defined in the DCR register. The FIFO logic also provides FIFO overrun and underrun signals for network management purposes. If received packets are flooding into the FIFO but the SLCT still does not have bus authority, the FIFO may be overrun. On the other hand, if a transmission begins before data are fed into the FIFO, it may be underrun. Either case results in a network error. FIFO overruns and underruns can be prevented by changing the values of the FIFO thresholds. Normally, the data in the FIFO cannot be read; reading FIFO data during normal operation may cause WAIT to be asserted and the system to hang. In loopback mode, however, the SLCT allows FIFO data to be read by byte in order to check the correctness of the loopback operation. Receive Logic The receive logic is responsible for receiving the serial network data and packing the data in byte/word sequence. The receive logic thus has serial-to-parallel logic in addition to network detection capability. The PENTIC+ accepts both physical addresses and group addresses (multicast and broadcast addresses). The SLCT extracts the address field from the serial input data. It then determines if the address is acceptable according to the configurations defined in the Receive Configuration Register (RCR). If the address is not acceptable, the packet reception is aborted. If the address is acceptable, the data packet is sent to the serial-to-parallel logic before being fed into the FIFO. After receiving a data packet, the SLCT automatically adds four bytes of data receive status, next packet pointer, and two bytes of receive byte count into the FIFO for network management purposes. The receive status contains the status of the incoming packet, so that the system can determine if the packet is desired. The next packet pointer points to the starting address of the next packet in the local receive ring. The receive byte count is the length of the packet received by the SLCT. Note that the receive byte count may be different from the "length" field specified in the Ethernet packet format. These four bytes of data will be transferred to the local buffer with the last batch of the local DMA. However, these four bytes are stored at the first four addresses of the packet. Transmit Logic The SLCT must be filled before transmission may begin. That is, the local DMA read must begin before the SLCT starts transmission. The SLCT first transmits 62 bits of preamble, then two bits of SFD, and then the data packet. The parallel-to-serial logic serializes the data from the FIFO into a data packet. After the data packet, the SLCT optionally adds four bytes of cyclic redundancy code (CRC) to the tail of the packet. A protocol PLA determines the network operations of the PENTIC+. Collision detection, random backoff, and auto retransmit are implemented in the transmit logic. The protocol PLA ensures that the PENTIC+ follows the IEEE 802.3 protocol. SNA Module The PENTIC+ also contains a serial network adaptor (SNA), which adapts the non-return-to-zero (NRZ) used in the core processor and host system to Manchester coded network symbols. Two kinds of interfacing signals are provided in the PENTIC+: an AUI interface for Ethernet and a coaxial
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W89C926 PENTIC+
interface for Cheapernet. The SNA contains three blocks: a phase locked loop (PLL), a Manchester encoder/decoder, and a collision decoder as well as crystal/oscillator logic.
TP or Coax
AUI Interface
PLL
Transmit Logic
L C E
Osc/ Crystal
Receive Logic
The Manchester encoder/decoder handles code interpretation between NRZ signals and Manchester coded signals. The PLL locks the receiving signals with an internal voltage control oscillator (VCO) so that network noise can be eliminated before the signals enter the core coprocessor. The collision decoder detects whether a collision has occurred on the network. The oscillator logic supplies the PENTIC+ with the required 20 MHz clock. This clock also supplies the SNA clocking system.
TWISTED PAIR INTERFACE MODULE FUNCTION
Transmit Driver There are two signals for data transmission: the true and complement Manchester differential data (TXO+/-). These two signals are resistively combined to form a pre-equalized differential pair, which is then passed to the twisted-pair cable via a transmitter filter and an optional common mode choke. Smart Squelch The main function of this block is to determine when valid data are present on the differential receiving inputs (RXI+/-). To ensure that impulse noise on the medium will not be taken to be valid data, this circuit adopts a combination of amplitude and timing measurements to determine the validity of the input signals. To qualify incoming data, the smart squelch circuitry monitors the signals for three peaks of alternating polarity that occur within a 400 nS window. Once this condition has been satisfied, the squelch level is reduced to minimize the noise effect and the chances of causing premature Start Of Idle (SOI) pulse detection. If the receiver detects activity on the receive line while packets are being transmitted, incoming data are qualified on five peaks of alternating polarity so as to prevent false collisions caused by impulse noise. The squelch function returns to its squelch state under any of the following conditions:
* * *
A normal SOI signal An inverted SOI signal A missing SOI signal
A missing SOI signal is assumed when no transitions have occurred on the receiver for 175 nS after a packet has arrived. In this case, a normal SOI signal is generated and appended to the data.
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Collision Detection The collision detection logic determines when transmit and receive signals occur simultaneously on the twisted pair cable. Collisions will not be reported when the device is in a link-fail state. The collision signal is also generated when the transceiver has detected a jabber condition or when the SQE test is being performed. SQE Test The Signal Quality Error (SQE) test is used to test the collision signaling circuitry in the twisted-pair transceiver module. After each packet transmission, an SQE signal is sent to the SLCT. The SLCT expects this signal and will flag an error if it does not exist. Jabber The jabber timer monitors the transmitter and disables the transmission if the transmitter is active for greater than 26.2 mS. The jabber will re-enable the transmitter after the SLCT has been idle for at least 420 mS. Link Integrity During periods of inactivity, link pulses are generated and received by both MAUs at either end of the twisted pair to ensure that the cable has not been broken or shorted. A positive, 100 nS link integrity signal is generated by the twisted-pair transceiver and transmitted on the twisted pair cable every 13 mS during periods of no transmission activity. The PENTIC+ assumes a link-good state if it detects valid link pulse activity on the twisted-pair transceiver receive circuit. If neither receive data nor a link pulse (positive or negative) is detected within 105 mS, the PENTIC+ enters a link-fail state. When a link-fail condition occurs, four consecutive positive link pulses (or eight negative link pulses) must be received before a link-good condition is assumed.
LCE CORE REGISTERS
This section lists the access addresses and access types of the LCE core registers. Refer to the W89C90 or W89C901 data sheet for more detailed information. Page 0 Address Assignments (PS1 = 0, PS0 = 0) RA0-3 00 01 02 03 04 05 06 07 08 Command (CR) Current Local DMA Address 0 (CLDA0) Current Local DMA Address 1 (CLDA1) Boundary Pointer (BNRY) Transmit Status Register (TSR) Number of Collisions Register (NCR) FIFO (FIFO) Interrupt Status Register (ISR) Current Remote DMA Address 0 (CRDA0) READ Command (CR) Page Start Register (PSTART) Page Stop Register (PSTOP) Boundary Pointer (BNRY) Transmit Page Start Address (TPSR) Transmit Byte Count Register 0 (TBCR0) Transmit Byte Count Register 1 (TBCR1) Interrupt Status Register (ISR) Remote Start Address Register 0 (RSAR0) WRITE
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Page 0 Address Assignments (PS1 = 0, PS0 = 0), continued
RA0-3 09 0A 0B 0C 0D 0E 0F
READ Current Remote DMA Address 1 (CRDA1) Reserved Reserved Received Status Register (RSR) Tally Counter 0 (Frame Alignment Errors) (CNTR0) Tally Counter 1 (CRC Errors)(CNTR1) Tally Counter 2 (Missed Packet Errors) (CNRT2)
WRITE Remote Start Address Register 1 (RSAR1) Remote Byte Count Register 0 (RBCR0) Remote Byte Count Register 1 (RBCR1) Receive Configuration Register (RCR) Transmit Configuration Register (TCR) Data Configuration Register (DCR) Interrupt Mask Register (IMR)
Page 1 Address Assignments (PS1 = 0, PS0 = 1) RA0-3 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F Command (CR) Physical Address Register 0 (PAR 0) Physical Address Register 1 (PAR 1) Physical Address Register 2 (PAR 2) Physical Address Register 3 (PAR 3) Physical Address Register 4 (PAR 4) Physical Address Register 5 (PAR 5) Current Page Register (CURR) Multicast Address 0 (MAR 0) Multicast Address 1 (MAR 1) Multicast Address 2 (MAR 2) Multicast Address 3 (MAR 3) Multicast Address 4 (MAR 4) Multicast Address 5 (MAR 5) Multicast Address 6 (MAR 6) Multicast Address 7 (MAR 7) READ Command (CR) Physical Address Register 0 (PAR 0) Physical Address Register 1 (PAR 1) Physical Address Register 2 (PAR 2) Physical Address Register 3 (PAR 3) Physical Address Register 4 (PAR 4) Physical Address Register 5 (PAR 5) Current Page Register (CURR) Multicast Address 1 (MAR 0) Multicast Address 1 (MAR 1) Multicast Address 2 (MAR 2) Multicast Address 3 (MAR 3) Multicast Address 4 (MAR 4) Multicast Address 5 (MAR 5) Multicast Address 6 (MAR 6) Multicast Address 7 (MAR 7) WRITE
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Page 2 Address Assignments (PS1 = 1, PS0 = 0) RA0-3 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F READ Command (CR) Page Start Register (PSTART) Page Stop Register (PSTOP) Remote Next Packet Pointer Transmit Page Start Address (TPSR) Local Next Packet Pointer Address Counter (Upper) Address Counter (Lower) Reserved Reserved Reserved Reserved Receive Configuration Register (RCR) Transmit Configuration Register (TCR) Data Configuration Register (DCR) Interrupt Mask Register (IMR) WRITE Command (CR) Current Local DMA Address 0 (CLDA0) Current Local DMA Address 1 (CLDA1) Remote Next Package Pointer Reserved Local Next Packet Pointer Address Counter (Upper) Address Counter (Lower) Reserved Reserved Reserved Reserved Reserved Transmit Configuration Reserved Reserved
Note: Page 2 registers should be accessed only for diagnostic purposes. They should not be modified during operation. Page 3 should never be modified.
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
PARAMETER Operating Temperature Storage Temperature Supply Voltage Input Voltage Output Voltage Lead Temperature (soldering 10 seconds maximum) ESD Tolerance SYMBOL TA TS VDD VIN VOUT TL ESD MIN. 0 -55 -0.5 VSS-0.5 VSS-0.5 2K MAX. 70 150 7.0 VDD+0.5 VDD+0.5 250 UNIT C C V V V C V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
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W89C926 PENTIC+
DC CHARACTERISTICS
Power Supply:
(VDD = 4.75V to 5.25V, VSS = 0V, TA = 0 C to 70 C)
PARAMETER Average Idle Supply Current Average Transmit Supply Current
Notes: 1. X1 = 20 MHz, VIN = VCC or GND. 2. X1 = 20 MHz, normal transmitting operation.
Note 1 Note 2
SYM. IAVI IAVT
CONDITIONS VDD = 5.25V VDD = 5.25V
MIN. -
MAX. 150 250
UNIT mA mA
Digital:
(VDD = 4.75V to 5.25V, VSS = 0V, TA = 0 C to 70 C)
PARAMETER Low Input Voltage High Input Voltage Low Output Voltage High Output Voltage Low Output Sink Current High Output Drive Current Low Output Sink Current* High Output Drive Current* Output 3-State Leakage Current AUI:
SYM. VIL VIH VOL VOH IOL1 IOH1 IOL2
IOH2 IOTR
CONDITIONS
MIN. VSS-0.5 2.0 2.4 4 2 -
MAX. 0.8 VDD+0.5 0.4 -
UNIT V V V V mA mA mA mA A
VDD = 4.75V, IOL = IOL-MIN VDD = 4.75V, IOH = IOL-MAX
VDD = 5.25V
-4 -2 10
* These are the parameteres for MSD0-7 and MSA0-15.
(VDD = 4.75V to 5.25V, VSS = 0V, TA = 0 C to 70 C)
PARAMETER Differential Output Voltage (TX+/) Differential Output Voltage Imbalance (TX+/-) Undershoot Voltage (TX+/-) Differential Squelch Threshold (CD+/-, RX+/-) Differential Input Common Mode Voltage (CD+/-, RX+/-)
SYM. VDD VOB VU VDS VCM
CONDITIONS With test load With test load With test load
MIN. +/-550 -175 2.0
MAX. +/-1200 40 100 -300 4.0
UNIT mV mV mV mV V
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Twisted Pair:
(VDD = 4.75V to 5.25V, VSS = 0V, TA = 0 C to 70 C)
PARAMETER RXI+/- Differential Input Resistance RXI+/- Open Circuit Input Voltage (bias) RXI+/- Differential Input Voltage Range RXI+/- Positive Squelched Threshold RXI+/- Negative Squelched Threshold RXI+/- Positive Unsquelched Threshold RXI+/- Negative Unsquelched Threshold TXO+/- Differential Output Voltage
SYM. RTI VTIB VTIV VTPS VTNS VTPU VTNU VTO
CONDITIONS
MIN. 3 -2.75
MAX. VDD-1.0 3.1 585 -300 350 -200 2.8
UNIT K V V mV mV mV mV V
VDD = 5V
-3.1 300 -585 200 -350
With test load
2.2
SWITCHING CHARACTERISTICS
Memory Support Bus Access (SRAM Access)
T15 Odd Address T10 T16 RCS T5 MSRD T9 T6
T1 MSAn Even Address
T2 MSDn (Read) T7 T8 MSWR T11 MSDn (Write) Valid T12 Valid
T3 Valid
T4
T14 T13
Valid
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W89C926 PENTIC+
SRAM (upper and lower values are for 70 nS and 15 nS SRAMs, respectively)
SYMBOL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 Read cycle time. MSA0-15 valid to MSD0-7 read data valid. MSD0-7 read data hold valid from MSA0-15 change. MSD0-7 read data hold from MSRD deasserted. RCS held valid after MSRD deasserted. MSA0-15 held valid after MSRD deasserted. RCS asserted to MSWR asserted MSWR pulse width RCS asserted to MSWR deasserted. MSA0-15 held valid after MSWR deasserted. MSD0-7 write data setup before MSWR asserted. MSD0-7 write data hold after MSWR deasserted. Even byte MSWR deasserted to odd byte MSWR asserted. (see note) T14 T15 T16 RCS held valid after MSWR deasserted. Even byte address invalid to odd byte address valid. (see note) Command recovery time. DESCRIPTION MIN. 70 15 5 3 0 0 5 3 5 3 0 0 60 15 60 15 5 3 35 10 5 3 10 5 5 3 0 0 30 10
Note: This timing is invalid for byte access, e.g, attribute memory reading on SRAM image.
MAX. 70 15 -
UNIT nS nS nS nS nS nS nS nS nS nS nS nS nS
nS nS nS
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Flash Memory Memory Support Bus Access (Flash Access)
T9 MSAn T3 T1 FCS T11 T4 T12
T2 MSRD MSWR
T10
T5 MSDn (Read)
T6
Valid
T7 MSDn (Write)
T8
Valid
SYMBOL T1 T2 T3 T4a T4b T5 T6 T7 T8 T9 T10 T11 T12a T12b T12c
DESCRIPTION MSA0-16 valid to FCS asserted. FCS asserted to MSRD , MSWR asserted. MSA0-16 held valid after MSRD , MSWR deasserted. FCS held valid after MSRD deasserted. FCS held valid after MSWR deasserted. MSRD asserted to read data valid. Read data hold from MSRD deasserted. Write data setup to MSWR deasserted. Write data hold from MSWR deasserted. Access cycle time Write pulse width FCS asserted to MSWR deasserted Write recovery time before read Read recovery time before write Consecutive same commands interval
MIN. 0 20 5 0 5 0 55 15 150 55 75 6 0 20
MAX. 60 -
UNIT nS nS nS nS nS nS nS nS nS nS nS nS S S nS
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Attribute Memory Access
HA0-16 REG REG low T12 T15 CE1,2 T13 T16 OE WE WAIT T3 HD0-7 (even) (Read) HD0-7 (even) (Write) T1 T2 T14
T19
T11
T10
T8
T9
T18
T17 Valid T4 T5 Valid T7 T6
SYMBOL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12
DESCRIPTION HA0-16, REG valid to OE, WE asserted
CE1 asserted to OE, WE asserted ,2
MIN. 30 0 80 30 0 0 20 20 180
MAX. 35 150 100 -
UNIT nS nS nS nS nS nS nS nS nS nS nS nS
OE, WE asserted to WAIT asserted OE asserted to HD0-7 read data valid (see note) HD0-7 write data setup before WE deasserted HD0-7 write data hold from WE deasserted HD0-7 read data disable from OE deasserted Read data setup before WAIT deasserted WAIT deasserted to OE, WE deasserted
CE1 hold valid from OE, WE deasserted ,2
HA0-16, REG hold valid from OE, WE deasserted HA0-16, REG setup to WE deasserted
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Attribute Memory Access, continued
SYMBOL T13 T14 T15 T16 T17 T18a T18b T19a T19b
DESCRIPTION
CE1 asserted to WE deasserted ,2
MIN. 180 150 10 10 300 250
MAX. 300 300 12 -
UNIT nS nS nS nS S nS nS nS nS
WE pulse width HA0-16, REG valid to read data valid (see note)
CE1 asserted to read data valid (see note) ,2
WAIT pulse width OE deasserted to next WE asserted WE deasserted to next OE asserted Read cycle time Write cycle time
Note: These timings are specified when the PENTIC+ does not assert WAIT .
Common Memory Access
HA0-16 REG T11
T16 REG high
T10 CE1,2 T12 OE WE WAIT T3 HD0-15 (Read) HD0-15 (Write) T4 Valid T14 Valid T6 T5 T1 T3 T13 T7 T8 T15 T9
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Common Memory Access, continued
SYMBOL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15a T15b T16a T16b
DESCRIPTION HA0-16, REG valid to OE, WE assert.
CE1 assert to OE, WE assert. ,2
MIN. 20 0 50 20 0 0 20 20 100 100 80 10 10 150 150
MAX. 35 75 12 -
UNIT nS nS nS nS nS nS nS nS nS nS nS nS nS S nS nS nS nS
OE, WE assert to WAIT asserts. HD0-15 write data setup before WE deasserts. HD0-15 write data hold from WE deasserts. HD0-15 read data disable from OE deasserts. Read data setup before WAIT deasserts. WAIT deasserts to OE, WE deassert.
CE1 hold valid from OE, WE deassert ,2
HA0-16, REG hold valid from OE, WE deassert HA0-16, REG setup to WE deassert
CE1 assert to WE deassert ,2
WE pulse width WAIT pulse width OE deassert to next WE assert WE deassert to next OE assert Read cycle time Write cycle time
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PCMCIA Bus Slave Access
HAn
T1 REG
T14
T2 CE T8
T15
OE , WE IORD , IOWR T3
T28
T16 T7
T17
IOIS16
T4
WAIT T5 T18 INPACK T6 T9 HDn (Read) T12 T11 HDn (Write) T13
T10
T19 MSAn Even Address Odd Address
T20 RCS
T21 MSRD
T23 MSDn (Read) T22 T25 MSWR T24 T26 MSDn (Write)
T27
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W89C926 PENTIC+
PCMCIA Bus Slave Access
SYMBOL T1a T1b T2a T2b T3a T3b T4 T5 T6 T7a T7b T8 T9a T9b T10 T11 T12 T13a T13b T14a T14b T15a T15b T16a DESCRIPTION HA0-16 & REG valid to OE, WE asserted
Note 2
MIN. 10 5 0 5 10 70
MAX. 35 35 40 100 50 0 0 -
UNIT nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS
HA0-16 & REG valid to IORD, IOWR asserted.
Note 3
CE1 asserted to OE, WE asserted. ,2 CE1 asserted to IORD, IOWR asserted. ,2
HA0-16 valid to OE, WE asserted. HA0-16 valid to IORD, IOWR asserted. HA0-16 valid to IOIS16 asserted.
Note 4
165 5 40 60 15 30 15 0 15 20 15
OE, WE, IORD, IOWR asserted to WAIT asserted.
Note 1
IORD asserted to INPACK asserted. IORD asserted to HD0-15 read data valid. OE asserted to HD0-15 read data valid. IORD, IOWR minimum width time.
Note 8 Note 6 Note 9
WAIT deasserted to HD0-15 memory read data valid. Note 1, 5 WAIT deasserted to HD0-15 I/O read data valid.
Note 1, 5
HD0-15 read data hold after OE, IORD deasserted. HD0-15 write data setup before WE deasserted. HD0-15 write data setup befor IOWR assert. HD0-15 write data hold after WE deasserted. HD0-15 write data hold after IOWR deasserted. OE, WE deasserted to REG deasserted.
Note 7
nS nS nS nS nS nS nS
IORD, IOWR deasserted to REG deasserted.
Note 7
OE, WE deasserted to CE1 deasserted. ,2 IORD, IOWR deasserted to CE1 deasserted. ,2 OE, WE deasserted to HA0-16 deasserted.
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Publication Release Date: January 1996 Revision A1
W89C926 PENTIC+
PCMCIA bus slave access, continued
SYMBOL T16b T17 T18 T19 T20 T21 T22 T23a T23b T24 T25 T26a T26b T27a T27b T28
DESCRIPTION IORD, IOWR deasserted to HA0-16 deasserted. HA0-16 deasserted to IOIS16 deasserted. IORD deasserted to INPACK deasserted. MSA0-14 asserted t0 WAITdeasserted.
CE1 asserted to RCS asserted. ,2
Note 1 Note 4
MIN. 20 -
MAX. 30 40 265 265 215 35 140 -
UNIT nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS
OE, asserted to ROE asserted.
Note 2
5 3
MSD odd byte read data valid to HD0-15 read data valid. MSD odd byte read data hold after MSRD deasserted. MSD odd byte read data hold after MSRD deasserted. MSA0-14 valid to MSWR asserted. second MSWR asserted before WAIT deasserted.
Note 1 Note.10
0 35 10 5 3 150
MSD write data setup before MSWR deasserted. MSD write data setup before MSWR deasserted.
Note.10
MSD write data hold after MSWR deasserted. MSD write data hold after MSWR deasserted. Note.10 Command deasserted to next command asserted
Notes: 1. This is the timing for insert wait states. WAIT is asserted if the core cannot service the access immediately; it will hold asserted until the core is ready, causing the system to insert wait states. 2. This is the timing for shared memory access. 3. This is the timing for I/O access. 4. IOIS16 is asserted for 16-bit I/O transfers. 5. Read data valid is referenced to WAIT when wait states are inserted. 6. If no wait states are inserted, read data valid can be referenced from OE, IORD. 7. REG is asserted for I/O access and it is deasserted for common memory access. 8. INPACK is asserted only for I/O read operation. 9. This is a shared memory access without bus contention. 10. This is the timing for SRAM-15.
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W89C926 PENTIC+
H/W Reset and Auto-Initialization Timing
T1
RESET
T3
CEn
T2
T4
IREQ
EECS/FCS sampling
EECS/FCS MSRD MSWR MSD0-7 MSAn
EECS/FCS floating
Auto-Loading
T5
T5
Flash Memory Loading Flash Auto-Loading (if EECS/FCS pulled high)
Flash Memory Loading
T7
T6
T6
Serial EEPROM loading EEPROM Auto-Loading (if EECS/FCS pulled low)
SRAM Write even byte
SRAM Write odd byte
SYMBOL T1 T2 T3 T4 T5 T6 T7
DESCRIPTION Reset pulse width Reset deasserted to EECS/FCS sampling Reset deasserted to CE1 asserted ,2 Nonvolatile memory auto-load time Flash memory auto-reading recovery time SRAM image auto-writing recovery time EEPROM auto-reading recovery time
MIN. 500 400 20 60 20 50
MAX. 10 -
UNIT nS nS mS mS nS nS nS
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Publication Release Date: January 1996 Revision A1
W89C926 PENTIC+
Serial EEPROM Timing
EECS T5 T4 T3 MSD2 (SCK) MSD1 (DI) T8 MSD0 (DO) T6 T7 T2
T1
Serial EEPROM Timing
SYMBOL T1 T2 T3 T4 T5 T6 T7 T8 DESCRIPTION EECS asserted to SK EECS hold from SK MSD2 OFF time MSD2 ON time MSD2 clock period MSD1 set up time to MSD2 high MSD1 hold time from MSD2 high MSD0 valid from MSD2 high MIN. 500 0 500 500 1 500 500 MAX. 500 UNIT nS nS nS nS S nS nS nS
AUI Transmit Timing (End of Transmit)
TTOI 1 TX+/1 TX+/0 1 0 0 TTOH
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W89C926 PENTIC+
SYMBOL TTOH TTOI
DESCRIPTION Transmit Output High Before Idle Transmit Output Idle Time
MIN. 200
MAX. 8000
UNIT nS nS
AUI Receive Timing (End of Receive)
1 RX+/RXI+ TEOP1 RX-/RXI1
0
0 TEOP0
RX+/RXI+ RX-/RXI-
SYMBOL TEOP1 TEOP0
DESCRIPTION End of Packet Received Hold Time after Logic "1" End of Packet Received Hold Time after Logic "0"
MIN. 200 200
MAX.
UNIT nS nS
Note: These parameters are specified by design and are not tested.
Link Pulse Timing
LPW T
LPI T
TXO+
TXO-
SYMBOL TLPI TLPW
DESCRIPTION Link Output Pulse Interval Link Output Pulse Width
MIN. 8 80
MAX. 24 120
UNIT mS nS
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Publication Release Date: January 1996 Revision A1
W89C926 PENTIC+
TPI Transmit Timing (End of Transmit)
1 TXO+ 0 1
TETH1
TXO-
TXO+
TETH1
TXO-
SYMBOL TETH1
DESCRIPTION End of Packet Transmitted Hold Time 1 (TXP/N)
MIN. 250
MAX.
UNIT nS
Note: This parameter is specified by design and is not tested.
AC TIMING TEST CONDITIONS
PARAMETER Supply Voltage (VDD/VSS) Temperature Input Test Pattern Levels (TTL/CMOS) Input Rise and Fall Times (TTL/CMOS) Input and Output Pattern Reference Level (TTL/CMOS) Input Waveform Level (Diff) Input and Output Waveform Reference Levels (Diff) 3-State Reference Levels TEST CONDITIONS 5V 0.25V 25 C/70 C GND to 3.0V 5 nS 1.3V -350 to -1315 mV 50% Point of the Differential Float (V) 0.5V
Note: The above specifications are valid only if the mandatory isolations are properly employed and all differential signals are taken to the AUI of the pulse transformer.
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W89C926 PENTIC+
Output Load
Vcc SW1 (Note 3)
0.1 F
DEVICE UNDER Input TEST
RL = 2.2K Output
CL (Note 1, 2)
Notes: 1. Load capacitance employed depends on output type: For 3SL, MOS, TPI, AUI: CL = 50 pF For 3SH, OCH: CL = 240 pF 2. Specifications which measure delays from an active state to a High-Z state are not guaranteed by production testing, but are characterized using 240 pF and are correlated to determine true driver turn-off time by eliminating inherent R-C delay times in measurements. 3. SW1 = Open for push-pull outputs during timing test. SW1 = VCC for VOL test. SW1 = GND for VOH test. SW1 = VCC for High-Z to active low and active low to High-Z measurements. SW1 = GND for High-Z to active high and active high to High-Z measurements.
Pin Capacitance
TA = 25 C, f = 1 MHz
SYMBOL CIN COUT
PARAMETER Input Capacitance Output Capacitance
TYP 7 10
UNIT pF pF
Derating Factor
Output timing is measured with a purely capacitive load of 50 pF or 240 pF. The following correction factor can be used for other loads (this factor is preliminary): Derating for 3SL, MOS = -0.05 nS/pF Derating for 3SH, OCL, TPI = -0.03 nS/pF
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Publication Release Date: January 1996 Revision A1
W89C926 PENTIC+
AUI Transmit Test Load
TX+ R = 78 27 H TX-
Note: In the above diagram, the TX+ and TX- signals are taken from the AUI side of the pulse transformer. The pulse transformer used for all testing is a 100H +/-0.1% Pulse Engineering PE64103.
UTP Transmit Test Load
TXO+
R = 1.21K 1%
UTP FILTER
R = 100 1%
TXO-
Note: In the above diagram, the UTP filter used for all testing is a Valor FL1012.
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W89C926 PENTIC+
PACKAGE DIMENSIONS
The PENTIC+ is packaged in a 100-pin TQFP for type II PC card applications. Detailed dimensions are shown below.
He E
Hd D
W89C926F
e
b
Symbol A1 @ A2 b C A2 C L D L1 Y A1 D E e Hd He L L1 Y @
Dimensions in inches Dimensions in mm 0.004 +/- 0.002 0.055 +/- 0.002 0.013 + 0.002 - 0.004 0.008 max 0.004 min 0.551 + 0.004 0.787 + 0.004 0.026 typ 0.630 + 0.004 0.866 + 0.004 0.024 + 0.006 0.039 typ 0.003 max 0 to 7 0.10 +/- 0.05 1.40 +/- 0.05 0.32 + 0.06 - 0.10 0.20 max 0.09 min 14.00 + 0.10 20.00 + 0.10 0.65 typ 16.00 + 0.10 22.00 + 0.10 0.60 + 0.15 1.00 typ 0.08 max 0 to 7
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Publication Release Date: January 1996 Revision A1
W89C926 PENTIC+
Headquarters
Winbond Electronics (H.K.) Ltd.
Winbond Electronics North America Corp.
Rm. 803, World Trade Square, Tower II, Winbond Memory Lab. No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Winbond Microelectronics Corp. Kowloon, Hong Kong Hsinchu, Taiwan Winbond Systems Lab. TEL: 852-27513100 TEL: 886-3-5770066 2727 N. First Street, San Jose, FAX: 852-27552064 FAX: 886-3-5792668 CA 95134, U.S.A. http://www.winbond.com.tw/ TEL: 1-408-9436666 Voice & Fax-on-demand: 886-2-7197006 FAX: 1-408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502
Note: All data and specifications are subject to change without notice.
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